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MCP2515
11.0
REGISTER MAP
reading and writing of data. Some specific control and
status registers allow individual bit modification using
The register map for the MCP2515 is shown in
determined by using the column (higher-order four
bits) and row (lower-order four bits) values. The regis-
ters have been arranged to optimize the sequential
the SPI Bit Modify command. The registers that allow
this command are shown as shaded locations in
TABLE 11-1:
Lower
Address
CAN CONTROLLER REGISTER MAP
Higher-Order Address Bits
Bits
0000 xxxx
0001 xxxx
0010 xxxx
0011 xxxx
0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
RXF0SIDH
RXF0SIDL
RXF0EID8
RXF0EID0
RXF1SIDH
RXF1SIDL
RXF1EID8
RXF1EID0
RXF2SIDH
RXF2SIDL
RXF2EID8
RXF2EID0
BFPCTRL
TXRTSCTRL
CANSTAT
CANCTRL
RXF3SIDH
RXF3SIDL
RXF3EID8
RXF3EID0
RXF4SIDH
RXF4SIDL
RXF4EID8
RXF4EID0
RXF5SIDH
RXF5SIDL
RXF5EID8
RXF5EID0
TEC
REC
CANSTAT
CANCTRL
RXM0SIDH
RXM0SIDL
RXM0EID8
RXM0EID0
RXM1SIDH
RXM1SIDL
RXM1EID8
RXM1EID0
CNF3
CNF2
CNF1
CANINTE
CANINTF
EFLG
CANSTAT
CANCTRL
TXB0CTRL
TXB0SIDH
TXB0SIDL
TXB0EID8
TXB0EID0
TXB0DLC
TXB0D0
TXB0D1
TXB0D2
TXB0D3
TXB0D4
TXB0D5
TXB0D6
TXB0D7
CANSTAT
CANCTRL
TXB1CTRL
TXB1SIDH
TXB1SIDL
TXB1EID8
TXB1EID0
TXB1DLC
TXB1D0
TXB1D1
TXB1D2
TXB1D3
TXB1D4
TXB1D5
TXB1D6
TXB1D7
CANSTAT
CANCTRL
TXB2CTRL
TXB2SIDH
TXB2SIDL
TXB2EID8
TXB2EID0
TXB2DLC
TXB2D0
TXB2D1
TXB2D2
TXB2D3
TXB2D4
TXB2D5
TXB2D6
TXB2D7
CANSTAT
CANCTRL
RXB0CTRL
RXB0SIDH
RXB0SIDL
RXB0EID8
RXB0EID0
RXB0DLC
RXB0D0
RXB0D1
RXB0D2
RXB0D3
RXB0D4
RXB0D5
RXB0D6
RXB0D7
CANSTAT
CANCTRL
RXB1CTRL
RXB1SIDH
RXB1SIDL
RXB1EID8
RXB1EID0
RXB1DLC
RXB1D0
RXB1D1
RXB1D2
RXB1D3
RXB1D4
RXB1D5
RXB1D6
RXB1D7
CANSTAT
CANCTRL
Note:
Shaded register locations indicate that these allow the user to manipulate individual bits using the Bit Modify command.
TABLE 11-2:
CONTROL REGISTER SUMMARY
Register
Name
BFPCTRL
Address
(Hex)
0C
Bit 7
—
Bit 6
—
Bit 5
B1BFS
Bit 4
B0BFS
Bit 3
B1BFE
Bit 2
B0BFE
Bit 1
B1BFM
Bit 0
B0BFM
POR/RST
Value
--00 0000
TXRTSCTRL
0D
—
—
B2RTS
B1RTS
B0RTS
B2RTSM
B1RTSM
B0RTSM --xx x000
CANSTAT
xE
OPMOD2 OPMOD1 OPMOD0
—
ICOD2
ICOD1
ICOD0
—
100- 000-
CANCTRL
xF
REQOP2 REQOP1 REQOP0
ABAT
OSM
CLKEN
CLKPRE1 CLKPRE0 1110 0111
TEC
REC
1C
1D
Transmit Error Counter (TEC)
Receive Error Counter (REC)
0000 0000
0000 0000
CNF3
28
SOF
WAKFIL
—
—
—
PHSEG22 PHSEG21 PHSEG20 00-- -000
CNF2
29
BTLMODE
SAM
PHSEG12 PHSEG11 PHSEG10 PRSEG2
PRSEG1
PRSEG0 0000 0000
CNF1
CANINTE
CANINTF
EFLG
TXB0CTRL
TXB1CTRL
TXB2CTRL
RXB0CTRL
RXB1CTRL
2A
2B
2C
2D
30
40
50
60
70
SJW1
MERRE
MERRF
RX1OVR
—
—
—
—
—
SJW0
WAKIE
WAKIF
RX0OVR
ABTF
ABTF
ABTF
RXM1
RSM1
BRP5
ERRIE
ERRIF
TXBO
MLOA
MLOA
MLOA
RXM0
RXM0
BRP4
TX2IE
TX2IF
TXEP
TXERR
TXERR
TXERR
—
—
BRP3
TX1IE
TX1IF
RXEP
TXREQ
TXREQ
TXREQ
RXRTR
RXRTR
BRP2
TX0IE
TX0IF
TXWAR
—
—
—
BUKT
FILHIT2
BRP1
RX1IE
RX1IF
RXWAR
TXP1
TXP1
TXP1
BUKT
FILHIT1
BRP0
RX0IE
RX0IF
EWARN
TXP0
TXP0
TXP0
FILHIT0
FILHIT0
0000 0000
0000 0000
0000 0000
0000 0000
-000 0-00
-000 0-00
-000 0-00
-00- 0000
-00- 0000
? 2003-2012 Microchip Technology Inc.
DS21801G-page 63
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